CAO

Q.    ‘Cycle Stealing’ is associated with
a)    Data transfer among registers
b)    DMA
c)    Pipelining
d)    Microprogramming

[DOEACC January, 2006]

Ans: b) DMA

Explaination:
 

Cycle stealing allows the DMA controller to transfer one data word at a time, after which it must return control of the buses to the CPU. The CPU merely delays its operation for one memory cycle to allow the direct memory I/O transfer to "steal" one memory cycle.